Table 312

+=====-========-========-========-========-========-========-========-========+ 
|  Bit|   7    |   6    |   5    |   4    |   3    |   2    |   1    |   0    | 
|Byte |        |        |        |        |        |        |        |        | 
|=====+=======================================================================| 
| 0   |                           Operation code (3Dh)                        | 
|-----+-----------------------------------------------------------------------| 
| 1   |   Logical unit number    |            Reserved               | RelAdr | 
|-----+-----------------------------------------------------------------------| 
| 2   | (MSB)                                                                 | 
|-----+---                                                                 ---| 
| 3   |                                                                       | 
|-----+---                        Logical block address                    ---| 
| 4   |                                                                       | 
|-----+---                                                                 ---| 
| 5   |                                                                 (LSB) | 
|-----+-----------------------------------------------------------------------| 
| 6   |                           Reserved                                    | 
|-----+-----------------------------------------------------------------------| 
| 7   |                           Reserved                                    | 
|-----+-----------------------------------------------------------------------| 
| 8   |                           Reserved                                    | 
|-----+-----------------------------------------------------------------------| 
| 9   |                           Control                                     | 
+=============================================================================+