Table 39

+=====-========-========-========-========-========-========-========-========+  
|  Bit|   7    |   6    |   5    |   4    |   3    |   2    |   1    |   0    | 
|Byte |        |        |        |        |        |        |        |        | 
|=====+==========================+========+========+==========================| 
| 0   | Source address           |   DC   |  Cat   | Source LUN               | 
|-----+--------------------------+-----------------+--------------------------| 
| 1   | Destination address      |   Reserved      | Destination LUN          | 
|-----+-----------------------------------------------------------------------| 
| 2   |                              Reserved                                 | 
|-----+-----------------------------------------------------------------------| 
| 3   |                              Reserved                                 | 
|-----+-----------------------------------------------------------------------| 
| 4   | (MSB)                                                                 | 
|- - -+---                Number of blocks                                 ---| 
| 7   |                                                                 (LSB) | 
|-----+-----------------------------------------------------------------------| 
| 8   | (MSB)                                                                 | 
|- - -+---                Source logical block address                     ---| 
| 11  |                                                                 (LSB) | 
|-----+-----------------------------------------------------------------------| 
| 12  | (MSB)                                                                 | 
|- - -+---                Destination logical block address                ---| 
| 15  |                                                                 (LSB) | 
+=============================================================================+